Design for Testability (DFT)
Introduction To DFT, DFT Basics
- ASIC Flow
- DFT Basics
- Chip Fabrication Process
- ATE Basics
Scan Insertion
- Scan architecture overview
- Scan Design Basics
- Scan Golden Rules
- Scan DRC Checks
- Scan Insertion
- Generate test protocol and understanding
Lock-Up Latches
Scan Compression
- Basics/Need for Compression
- Compression Techniques
- On-Chip-Clocking
- At-Speed Testing
Hierarchical Scan and Boundary Scan
- Hierarchical Scan
- Bscan (Boundary Scan)
- Jtag
Introduction To ATPG, Atpg Basics
- ATPG Basics
- Faults Collapsing
- ATPG Algorithms
Fault Models, Fault Classes
- Fault Models,
- ATPG DRC,
- Fault Classes,
- ATPG
Pattern Generation And Simulations
- Simulation Basics
- Atpg Simulations
- Coverage Improvement
Speed ATPG And Simulations
- At-Speed ATPG
- LOC and LOS
- At-Speed Simulations
Simulations And Debugging
- Scan Simulations Debug
- Diagnosis Flow
- Fault Simulation
BIST
- BIST Architecture,
- Memory BIST
- Logic BIST
Project
- A block-level design will be given as project, in which you need to insert scan and generate patterns, to get the required test coverage.
VLSI professionals can build a rewarding and challenging career with DFT Online Course and DFT Training.
Design For Testability, commonly called as DFT is a specialization in the SOC design cycle, which facilitates design for detecting manufacturing defects. DFT Course is different than functional verification, which tests the functionality of the design and is popularly known as Design Verification.
VLSI DFT Course online has evolved as a specialization in itself over period of time, with the increase in size & complexity of chips, facilitated by the advancement of manufacturing technologies like 10nm, 7nm, DFT Engineers works on introducing various test structures as part of the design flow, on increasing the testability of logic, pads, memories, interconnects.
DFT Course Online covers different techniques like Scan Insertion to test the combinational & sequential logic, BIST to test the memories, JTAG to test the PADS. etc. Using ATPG Techniques test patterns are generated on the scan inserted design. Generated patterns are simulated and debugged in case of any failures.
VLSI DFT Course Online is designed as per industry requirements, covering SCAN, ATPG, BIST, JTAG along HandsOn labs and multiple projects covering all DFT Techniques.
Course | DFT Training |
---|---|
Duration | 24 weeks 6 weeks of basics training 18 weeks of core DFT training |
Next Batch | Â |
Schedule | Weekend batch: Saturday & Sunday(9AM – 5PM IST) Full week batch: 6 days/week, 9AM – 1PM, Friday break |
New batch | every 8 weeks |
Tool | Mentor Graphics Tessent Synopsys DFTAdvisor and Tetramax |
Mode of training | Online training – 100% online Classroom training – 50% of course in classroom and rest online |
 | e-learning course for self paced learning with weekend lab sessions |
Tool Access | 24×7 access for the complete course duration |
Batch Size | 15 |
Assignments | 20 |
Course Highlights
- 1-1 Dedicated Mentor Support
- Â 24/7 Tool Access
- Multiple mock interviews
- Industry Standard Projects
- Support with resume update