Universal Memory Controller using SV & UVM

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Universal Memory Controller Functional Verification Training

  • Universal memory controller and memory detailed overview
  • Design specification
  • Listing down features, scenarios
  • Developing testplan
  • Testbench architecture
  • Testbench component coding
    • Functional coverage coding
    • Register model coding and integration
    • Assertion development
  • Testbench component integration
  • Sanity Testcase coding
  • Functional Testcase coding
  • Regression setup using Python
  • Regression debug
  • coverage report generation and analysis
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Universal Memory controller design support various types of memories like SRAM, SDRAM, Flash, ROM and Synchronous memory devices. It supports 8 chip selects with configurable memory sizes and timing behavior. This project provides student with detailed exposure to complete project flow starting from reading the specification till coverage report generation and regression analysis. Student will get exposure to regression setup, coverage analysis and scoreboard development. This project is also good for working professionals whose work is generally confined to limited aspects of verification flow and want to get quick hands on exposure to complete flow.

CourseUSB2.0 protocol and USB2.0 core verification using SV & UVM
DurationLive training : 5 weeks
eLearning : 35 hours
Next Batch 
Mode of TrainingLive training for minimum of 10 participants
e-learning for self paced learning
FeeLive training : INR 10,000 +GST
eLearning : INR 9,000 + GST
CertificateIssued
Course Highlights
  • 1-1 Dedicated Mentor Support
  •  24/7 Tool Access
  • Multiple mock interviews
  • Industry Standard Projects
  • Support with resume update