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Home
Company
Who we are
Leadership team
Services
Training Courses
Freshers
Functional / ASIC Verification
Physical Design
FPGA System designs & Verification
Design for Testability (DFT)
Custom / Analog Layout
Embedded System
Working Professionals
RTL Designs and Integration
Functional Verification for Experienced
Advanced Physical Design
Design for Testability (DFT)
Custom and Analog Layout
Synthesis and STA
IR Drop analysis using RedHawk
Protocol Courses
PCle Gen5
AMBA (AXI, AHB, & APB)
DDR1 to DDR4, LPDDR1 to LPDDR4
DDR5
AMBA CHI Training
USB2.0 & USB3.x
USB4
SPI, I2C and UART
ACE Protocol
Display Port
NVMe
CXL Training
Short Term Courses
Verilog
System Verilog
UVM Course
UVM Advanced Course with Multiple Projects
System Verilog Assertions and Coverage
UVM Register Model Training
LEC Formal
Lint and CDC
Formal Property Verification
Advanced Digital Design
SoC
SOC Design and Verification
Functional Verification Debug Technique
ARM V8 Architecture
UPF Power Aware Verification
RISC-V ISA
Gate Level Simulation(GLS)
Scripting
PERL Training
Python Training
Linux Training
TCL Scripting Training
GVIM Training
Shell Scripting Training
Interview Preparation Courses
Functional Verification Interview Preparation
Physical Design Interview Preparation
DFT interview Preparation
Embedded System Interview Preparation
FPGA Interview Preparation
Functional Verification Projects
DMA Controller Verification Using SV & UVM
Ethernet MAC Verification using SV & UVM
Universal Memory Controller using SV & UVM
AXI2OCP Bridge Verification using SV & UVM
USB2.0 Core Verification using SV & UVM
BTech & MTech Internships
MTech VLSI Projects & Internship
MTech Embedded System & Internship
VLSI short Term Internship
Embedded System Summer Internship
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