Physical Design
Essentials of Linux
- Introduction to Linux
- Command Line Operators
- File Operations
- Processes
- Text Editors
- Text Manipulating
- Network Operations
- Special Keystrokes
- Assessment and Quizzes
Digital Design
- Number System, Boolean Algebra, SOP and POS, K-Map
- Combinational circuits
- Sequential circuits
- Finite State machines
- Frequency Division
- Setup and Hold time checks
- Advance Design Issues: Metastability, Noise Margins, Power, Fanout, Timing
- Considerations
- FIFO Depth Calculation
- Assessment and Quizzes
CMOS Devices and Technology
- Electronic Devices, Power Sources, Thevenin and Norton Theorem
- Semiconductors Device Physics: Atomic Structure, Electronic Configuration, Doping, Diode –Biasing and VI Characteristics
- MOSFET: Regions of operation, VI Characteristics
- Function implementation using CMOS
- Stick Diagram and Layout
- Second order effects: Body Effect, Channel length modulation, Punch through, subthreshold conduction, DIBL
- Process Technology: Clean Room, Wafer manufacturing, Oxidation, Diffusion, Ion
Implementation, Lithography - Assessment and Quizzes
Verilog HDL
- Introduction to Verilog
- Applications of Verilog HDL
- Verilog HDL language concepts
- Verilog language basics and constructs
- Data Types, Nets and registers, Arrays
- Verilog Operators: Logical operators, Bitwise and Reduction operators, Concatenation and conditional operators, Relational and arithmetic, Shift and Equality operators, Operators precedence.
- Type of assignments: Continuous assignments, Inter/Intra assignments, Blocking and Nonblocking assignments, Execution branching, Tasks and Functions
- Finite State Machine (FSM): Basic FSM structure, Moore Vs Mealy, Common FSM coding styles, Registered outputs
- Assessment and Quizzes
Synthesis
- ASIC Design flow and role of Synthesis
- Synthesis flow
- writing timing constraints in SDC format
- constraining the design for timing
- power, area goals, set optimization techniques
- synthesize the design
- generate and analyze the reports, save the netlist and SDC
Logic Equivalence Checking (LEC)
- Formal Verification
- Understanding & Matching compare points
- Debugging nonequivalent points What-If Analysis
TCL Scripting
Features of TCL and Applications. TCL commands, Variables, arithmetic expressions, comments, identifiers, reserved words, data types, decisions, loops, arrays, strings, file I/O and procedures.
Scripting exercises from simple problems to complex problems, in an incremental manner and
using tools like Prime Time, ICC2.
Introduction to Physical Design, Data Preparation and Sanity Check
Introduction to physical design and Physical Design Flow, Data preparation: Files required for PD (Netlist, SDC, Libraries, Technology files, TLU+), the contents of each input file, Sanity checks.
Floorplan
Goals of Floor planning, different aspects of floor planning, Rectangle/Rectilinear floorplans, Die
size estimation (Core Utilization, Aspect ratio), IO placement, macro placement and guidelines,
channel-width estimation
Power Routing
Goals of Power Routing, Power distribution structure (Rings, straps and follow-pin/std cell rail), metal stack information, power planning methodology, IR drop analysis, types of power
consumption. Why Low power and low power techniques. Electro-migration analysis.
Placement
Goals of Placement, types of placements, pre-place (Endcap, Tap & I/O Buffer) cells, placement optimization, congestion analysis, timing analysis, Tie-cells, High-Fanout Net Synthesis, Scan chain re-order, Path Grouping and creating Bounds.
Timing Analysis (Pre-Layout STA) & Optimization
STA Overview and concepts, Basic timing checks (setup, hold), understanding timing
constraints (SDC), timing corners, timing report analysis.
General optimization techniques, typical causes for timing violations and strategies for fixing the
same, Pre-CTS optimization to Fix setup violation
Clock Tree Synthesis (CTS)
Goals of CTS, Types of Clock-tree, constraints for CTS, building clock tree, Analyze the results,
Post-CTS optimization: Fixing Setup and Hold violations.
Routing
Goals of Routing, Stages of Routing: Global Routing, Track assignment and Detail Routing,
Routing options, Fixing of routing violations (DRC, LVS), post route optimization, issues in routing and guidelines for optimum routing results.
Post Layout STA
Post layout STA using SPEF, Multi-Mode Multi Corner STA, Derating factors, PVT, OCV Variations, Crosstalk Analysis
ECO Flow
What is ECO, Types of ECO, Timing & Functional ECO, Performing the ECO placement and routing.
VLSI Physical Design course, specially designed for fresh graduates to get comprehensive training to start
a career in VLSI Industry as a Physical Design Engineer. The course covers the latest industry requirements
and is covered by trainers experienced in Physical Design.
The course begins with introduction to Linux, Fundamentals to CMOS and Digital Electronics, Digital
design using Verilog.
The course comprehensively covers Synthesis, Logical Equivalence Check (LEC), Physical design flow
including Floorplan, Powerplan, Placement, Clock Tree Synthesis & Routing, Static Timing Analysis,
Physical Verification.
2 projects will be covered during the course using 14nm/28nm library. Lab
Course is offered in 2 modes:
- Full week course (for freshers)
- 9AM to 1PM on 6 days/week (Friday is break)
- Weekends only course (for working professionals)
- 9AM to 5:30PM on both Saturday & Sunday
- Session timings might differ for students from US and other times zones.
- 9AM to 5:30PM on both Saturday & Sunday
Course | Physical Design Training |
---|---|
Duration | 6.5 months |
Course start date | Â |
Schedule | Â |
Freshers | 6 days/week 9:30AM – 1:30PM IST |
Working professionals | Saturday & Sunday Theory session : 9:30AM to 1:30PM Lab session   : 2:30PM to 6PM (different timings for students from US and Canada) |
New batch starts | Every 6 Weeks |
Tools | Synopsys ICC II, Primetime, StarRC, Design Compiler, ICV |
Mode of training | Classroom training Live online training eLearning mode with dedicated mentor for doubt clarifications |
Fee | Live training : 63K + GST eLearning   : 45K + GST |
Tool Access | 24×7 Tool access for complete course duration |
Certificate | Issued based on 50% assignment completion as criteria |
Batch Size | 25 |
Assignments | 20 |
Placement support | 100% support till student gets a job. |
Trainer | Experienced trainers working on latest technologies in top MNCs. |
Course Highlights
- 1-1 Dedicated Mentor Support
- Â 24/7 Tool Access
- Multiple mock interviews
- Industry Standard Projects
- Support with resume update