Join the Team
Join our Dynamic Growing Team
1. Circuit Design (1 to 10 Years)
- Experience in designing of analog blocks for power-management like LDO, BGR, UVLO, Charge-pump, Osc, Gate Drivers etc.
- Strong communication skills & team player
- Strong knowledge in analog circuit design & simulations
- Good knowledge of Analog layout concepts and able to guide layout team with layout constraints
- Hands-on experience in Cadence’s tool flow
- Good communication skills English
2. Analog Layout (1 to 10 Years)
- Work independently on block level and chip level Analog layout designs, coordinating with circuit designers and layout leads.Â
- Proficient in FinFET layouts Â
- Custom layout experience in high-frequency circuits such as LNAs, BBF, BIAS, Mixers, VCOs, DAC, ADC, PLL, LDO, etc.Â
- Familiarity with Cadence-Virtuoso, PVS, ASSURA, and Calibre tools.Â
- Ability to effectively work and communicate with global engineering teams.Â
- Good communication skills EnglishÂ
3.Physical Design (1 to 10 Years)
- 2+ years of experience in Physical Design for 14nm or less technologyÂ
- Responsible for block level STA/timing closure / PNR.Â
- Well versed with Synopsys Prime Time or Cadence Tempus or equivalent timing closure toolÂ
- Good communication skills English
4. Digital Verification ( 1 to 10 Years)
-
- Strong Verilog, SV & UVM skills 
- Good knowledge in any of the protocols like Ethernet/PCIE/USB/DDR/AXI/SATA/MIPI 
- Experienced in developing test bench components, writing tests and coverage tuning 
- Digital Design and Verification Verilog/System-verilog 
- Good scripting knowledge using PERL / PYTHON