AMBA (AXI, AHB, & APB)

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AMBA (AXI, AHB, and APB)

  • Introduction to on-chip protocols
    • Protocol overview
    • AXI revisions
    • AXI based system architecture
    Signal descriptions
    • Global signals
    • Write address channel signals
    • Write data channel signals
    • Write response channel signals
    • Read address channel signals
    • Read data channel signals
    • Low power interface signals
    Signal Interface requirements
    • Basic write and read transactions
    • Relationship between channels
    • Transaction structure
    Transaction attributes
    • Transaction types and attributes
    • AXI3 memory attribute signalling
    • AXI4 changes to memory attribute signalling
    • Memory types
    • Mismatched memory attributes
    • Transaction buffering
    • Access permissions
    Multiple transactions
    • AXI transaction identifiers
    • Transaction ID
    • Transaction ordering
    AXI4 Ordering model
    • Definition of ordering model
    • Master ordering
    • Interconnect ordering
    • Slave ordering
    • Response before final destination
    Atomic accesses
    • Single-copy atomicity size
    • Exclusive accesses
    • Locked accesses
    • Atomic access signaling
    AXI4 additional signaling
    • QoS signaling
    • Multiple region signaling
    • User-defined signaling
    Low-power interface
    • Low power interface signals
    • Low power clock control
    Default signaling and Interoperability
    • Interoperability principles
    • Major Interface categories
    • Default signal values
  • VIP architecture
  • VIP components
  • VIP types
    • Master, Slave
    • Active, Passive
  • VIP test scenario listing down
  • VIP component coding
    • Driver, Generator, Monitor, Coverage, Environment
    • Interface, transaction, Slave model, assertions
  • Testbench integration
    • Testcase coding
    • Simulations and waveform analysis
  • Functional coverage analysis
  • Assertion coding and analysis

Enhance AXI3 VIP for AXI4 additional features

  • QoS signaling
  • Multiple region signaling
  • User-defined signaling
  • Low power interface
  • UVC architecture
  • UVC components
  • UVC types
    • Master, Slave
    • Active, Passive
  • UVC test scenario listing down
  • UVC component coding
    • Driver, Sequencer, Monitor, Coverage, Environment
    • Interface, transaction, Slave model, assertions
  • Testbench integration
    • Testcase coding
    • Simulations and waveform analysis
  • Functional coverage analysis
  • Assertion coding and analysis
  • APB protocol introduction
  • Signal descriptions
  • Transfers
  • Operating states

Introduction

  • About the protocol
  • AHB revisions
  • Operation

Signal Descriptions

  • Global signals
  • Master signals
  • Slave signals
  • Decoder signals
  • Multiplexor signals

Transfers

  • Basic transfers
  • Transfer types
  • Locked transfers
  • Transfer size
  • Burst operation
  • Waited transfers
  • Protection control
  • Memory types
  • Secure transfers

Bus Interconnection

  • Interconnect Address decoding Read data and response multiplexor

Slave Response Signaling

  • Slave transfer responses

Data Buses

  • Data buses
  • Endianness
  • Data bus width

Clock and Reset

  • Clock and reset requirements

Exclusive Transfers

  • Introduction
  • Exclusive Access Monitor
  • Exclusive access signaling
  • Exclusive Transfer restrictions

Atomicity

  • Single-copy atomicity size
  • Multi-copy atomicity

User Signaling

  • User signal description
  • User signal interconnect recommendations
  • Develop APB UVC for master and slave
  • APB master UVC validation using slave UVC

AMBA Protocol training is structured to enable engineers gain perfection in AXI, AHB & APB protocols. Majority of designs are based on ARM architecture. All ARM architectures are based on AMBA protocols(AXI, AHB and APB), which makes it essential for every design & verification engineer to have detailed understanding of these protocols. SoC design debug and testbench component coding in most cases involves either AXI and/or AHB protocols, and also majority of interviews are focused on candidate familiarity with AXI or AHB protocol. All this makes it essential for every VLSI engineer to have good working knowledge of these protocols.

AMBA Protocol training course focuses on teaching protocol concepts, features, timing diagrams from basic to advanced for AXI4.0, AHB2.0 and APB. Course also focus on teaching protocol testbench development concepts. Student has flexibility to choose specific protocol as well.

CourseAMBA Protocol training, AXI VIP, AHB UVC and APB UVC Development
DurationLive training : 6 weeks
eLearning : 45 hours
Course Start date 
Schedule 
Freshers6 days/week
4 hours/day, 9:30AM to 1:30PM
Working professionalsSaturday & Sunday
9:30AM – 1:30PM India time
Access to all the session recorded videos for entire course duration.
New batch startsEvery 10 Weeks
FeeLive training : INR 11,000 + GST
eLearning    : INR 9,500 + GST
ToolQuestasim & VCS
Mode of trainingLive training for minimum of 10 participants or corporate training.
eLearning with dedicated mentor for doubt clarifications.
Tool Access24×7 access to tool  for entire course duration
Assignments5
Course Highlights
  • 1-1 Dedicated Mentor Support
  •  24/7 Tool Access
  • Multiple mock interviews
  • Industry Standard Projects
  • Support with resume update