• Combinational logic
  • Number systems
  • Radix conversions
  • K-maps, min-terms, max terms
  • Logic gates
  • Realization of logic gates using mux’s and universal gates
  • Compliments (1/2/9/10’s complement)
  • Arithmetic operations using compliments
  • Boolean expression minimization, Dmorgan theorems
  • POS and SOP
  • Conversion and realization
  • Adders
    • Half adder
    • Full adder
  • Subtractor
    • Half subtractor
    • Full subtractor
  • Multiplexers
  • Realizing bigger Mux’s using smaller Mux’s
  • Implementing Adders and subtractors using Multiplexers
  • Decoders and Encoders
  • Implementing Decoders and Encoders using Mux and Demux
  • Bigger Decoder/Encoder using smaller Decoder/Encoder
  • Comparators
  • Implementing multi bit Comparators using 1-bit Comparator
• Sequential logic
  • Latch, Flipflop
  • Latch, Flipflop using Gates or Mux’s
  • Different types of FFs
  • FF Truth table
  • Excitation tables
  • Realization of FF’s using other FF’s
  • Applications of FF’s, Latches
    • Counters
    • Shift registers
    • Synchronizers for clock domain crossing
    • FSM’s
    • Mealy, Moore FSM
    • Different encoding styles
    • Frequency dividers
    • Frequency multiplication
  • STA
    • Setup time, Hold time, timing closure
    • fixing setup time and hold time violations
    • Launch flop, capture flop

• SOC Architecture overview
• SOC design concepts
• SOC verification concepts
• SOC Components
• SOC use cases
• SOC Testbench architecture
• SOC Test Case coding
• SOC verification differences with module verification

• Installing Linux platform in Windows
• Linux basics
• Linux versus Windows
• Linux Terminal
• File and Directory management
• Changing file permissions
• Absolute path and relative path
• Working with directories
• GVIM – major keyboard shortcuts
• Text display commands
• Root configuration files
• Environment variables
• Text processing commands
  • grep, fgrep
  • xargs
  • SEd
  • AWK
  • Pipes and filters
• Connecting to server
• Process management
• LSF
• Ping
• FTP
• CTAGs
• File compress and extract
• Softlinks

• Verilog language basics
• Verilog : How the language evolved?
• Verilog execution using Modelsim
• Verilog constructs
  • Literals
  • Data types
  • Operators
  • Continuous assignments
  • Procedural timing controls
  • task and functions
  • system task and function
  • modeling memories and FSM
  • Parameters
  • Port connections
  • Procedural blocks
  • Sensitivity list
  • State machines
  • timescale
  • Verilog timing regions
  • process
  • Blocking and nonblocking statements
  • Inferring combinational and Sequential logic
  • fork join
  • Race conditions
  • Synthesis examples
  • Inter and Intra delay statements
  • Pipelining
  • PLI
  • compiler directives

• DFF coding using gate level, behavioral
• Counters
  • Up counter
  • Ring counter
  • Johnson counter
• Memory design and verification
• Memory Verilog coding
• Front door access
• Back door access test case coding
• Test case coding and understanding waveforms
• FIFO – Synchronous FIFO and Asynchronous FIFO
  • Synchronous FIFO
  • Asynchronous FIFO
• Finite state machines
  • Mealy and Moore style
  • Implicit and Explicit styles of coding.
• Pattern detector – Overlapping, Non-Overlapping, Dynamic
  • Overlapping
  • Non-Overlapping
  • Dynamic
• Traffic light controller
• APB protocol
• Interrupt controller
• SPI controller
• CRC generation

• PAL, CPLD and FPGA basics
• FPGA Design Flow

• Internals of FPGA and CPLD
• Logic implementation
• FPGA Architectures of various FPGA vendors
• Anti-fuse and SRAMS
• Logic elements and Look-up Tables
• Dedicated multipliers
• Distributed RAM
• Shift registers
• MMCM
• Kintex
• Zynq
• Virtex Architectures

• Introduction and usage of IP cores·

• Modalism/Icarus Verilog simulation
• Design Synthesis

• Design constraining and pin locking
  • Timing analysis
  • slack calculation
  • Data loss due to large skew
  • Maximum skew calculations with examples
  • Period constraints
  • Area and Power Constraints
• Static Timing Analysis
• FPGA programming
• Translate
• Map
• Floor plan
• Place and Route
• Post map and Post P&R simulation
• XDC constraints
• Reading and analysing reports-post synthesis
• Post map simulation
• Post P·&R simulation
• Configuring FPGAs
• FSM Extraction

• Timing Simulation using Modalism/Icarus Verilog
• Programming using JTAG

• Debugging techniques
  • Debugging using chip scope and Logic analyzers
  • Protocols on FPGA
  • High Speed SERDES
• Identification of the issues/resolving

• FPGA SDK environment
• FPGA Device selection

• PERL Interpreter
• Variables
• File management
• Subroutines
• Regular expressions
• Object oriented PERL
• PERL modules

• Facing interviews effectively
• industry work culture
• Group discussions

100+ detailed assignments covering all aspects from VLSI Flow, SOC Design, Verilog, Advanced digital design, System Verilog, AXI protocol, VIP Development, RTL debug, UNIX and PERL scripting.