UVM Advanced Course with Multiple Projects
Verification Methodologies: UVM & OVM
- AHB Interconnect verification project used as reference design to learn UVM & OVM
- AHB Interconnect will be verified from scratch while teaching all aspects of UVM
- What is UVM? Need for a methodology?
- How UVM evolved?
- OVM, AVM, RVM, NVM, eRM
- UVM class library
- Classification of base classes in various categories
- OOP basics
- Encapsulation
- Inheritance
- Polymorphism
- Parameterized classes
- Parameterized macros
- Static properties and static methods
- Abstract classes
- Pure virtual methods
- How above aspect correlates with UVM implementation.
- UVM Class Library, Macros, Utilities
- Detailed overview of important UVM base classes, Macros and Utility classes.
- UVM TB Architecture
- Setting up a UVM based testbench for APB protocol from scratch.
- Significance of uvm_root in UVM based testbenches.
- run_test, how it starts whole TB flow.
- Command line processor
- Reporting classes
- Uvm_report_object
- Uvm_report_handler
- Uvm_report_server
- Detailed examples on use of methods in these classes.
- Objections
- UVM Factory
- Configuration DB, Resource DB
- Detailed usage of both data bases.
- How config_db is related to resource_db?
- Using config_db to change the testbench architecture.
- TLM1.0
- Push
- Pull
- FIFO
- Analysis
- Complex example on AHB to AXI transaction conversion.
- Simulation Phases
- UVM common phases
- Scheduled phases
- Sequences, Sequencers
- Default sequence
- p_sequencer
- m_sequencer
- Test case development
- Different styles of mapping testcase to sequence
- Using default sequence and scheduled phases
- Using sequence start method
- Different styles of mapping testcase to sequence
- Configuring TB Environment
- Advanced aspects of developing a highly configurable test bench environment.
- Concept of knobs of test case scenario generation
- Using top level parameters to control the overall TB architecture
- AHB Protocol and AHB UVC development
- Coding from scratch with detailed explanation of each aspect.
- Setting up a highly configurable UVC to meet different TB requirements.
- Different testbench component coding
- Monitor
- Coverage
- Scoreboard
- Checkers
- Assertions
- Different styles of sequence development
- `uvm_do
- Start_item and finish_item
- Using existing sequences
- Sequence library
- Creating complex test cases using sequence library
- Virtual Sequencer, Virtual sequences
- Different types of sequences used in test benches
- Reset sequence
- Power up sequence
- interrupt handling sequence
- DMA handling sequence
- FSM verification sequence
- Layered sequence development
- How to create multiple layers of sequences
- Creating complex test cases using layered sequences
- Virtual sequence library
- Creating test cases using virtual sequence library
- Synchronization classes
- uvm_barrier
- uvm_event
- Container classes
- Policy classes
- uvm_printer
- uvm_recorder
- uvm_packer
- uvm_comparer
- Comparators
- In order comparator
- Algorithmic comparator
- TLM2.0
- Blocking transport
- Non-blocking transport
- Register Layer development for USB2.0 core
- Note: Doesn’t involve USB2.0 core verification
- Connecting multiple UVCs
- How to setup a complex testbench environment with multiple UVC’s connected.
- uvm_heartbeat
- How to check test bench status using heartbeat
- uvm_report_catcher
- How to handle error testcases using report catcher
- Phase jumping
- uvm_domain
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AHB UVC Development
- AHB Protocol
- AHB System architecture
- Features
- Signals
- Timing Diagrams
- AHB UVC Architecture
- AHB UVC Component Coding
- AHB UVC Sequence & Test Development
AHB Interconnect Functional Verification
- AHB Interconnect Testbench Architecture
- AHB UVC & APB UVC in Interconnect Testbench setup
- Verification Component Coding
- Testcase & virtual sequence Development & Debug
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USB2.0 Register Layer
- Listing down registers
- Creating Register Model
- Integrating Register Model in to Testbench
- Using Register Model to create tests
- Using Register Model in scoreboard
Course Assignments
- UVC Development for AXI Protocol
- PCIe LTSSM FSM Verification
- Register Model Development for SPI Core
UVM training is a 9 weeks course provides participants with in depth exposure to all the UVM constructs using practical use case examples. Course includes 15+ assignments covering all the constructs in depth.
Course also includes multiple hands on projects based on APB, AHB test bench development. Also includes TB development for AHB interconnect model.Â
| Course | UVM advanced with multiple projects – Deep dive |
|---|---|
| Duration | Live training : 9 weeks eLearning    : 65 hours |
| Next Batch | Â |
| Schedule | Â |
| Freshers | 6 days/week, 4 hours/day |
| Working professionals | Saturday & Sunday(9AM – 1PM IST) Access to all course recorded videos for entire course duration |
| Tool | Questasim & VCS |
| Mode of training | Classroom training & Live online training Course can also be done in hybrid mode. |
| Â | eLearning with dedicated mentor for doubt clarifications. |
| Fee | Live training : INR 18K + GST eLearning : INR 15K + GST |
| Batch Size | 25 |
| Assignments | 16 |
Course Highlights
- 1-1 Dedicated Mentor Support
- Â 24/7 Tool Access
- Multiple mock interviews
- Industry Standard Projects
- Support with resume update