System Verilog Assertions and Coverage

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System Verilog Assertions and Coverage

  • Constraints format
  • Constraints type
    • Simple
    • distribution
    • implication
    • if-else
    • iterative
    • variable ordering
    • soft
    • unique
  • Inline constraints
  • Constraints for queue randomization
  • Constraints virtual nature
  •  
  • Randomization in class, module
  • rand, randc
  • randcase
  • Multiple hands on examples on Constraints and Randomization
  • Chip select example using multiple inter related constraints
  • new significance for randc
  • Constrained random verification
  • Directed verification
  • What is functional coverage?
  • Need for functional coverage
  • Where FC comes in functional verification flow?
  • How to implement FC?
  • Different types of FC?
  • Integrating Functional coverage in Test bench
  • functional coverage hierarchy
  • Different types of coverpoints – simple, cross, transition
  • Different types of bins – normal, illegal, ignore
  • coverage calculation
  • coverage options
    • auto_bin_max
    • weigth
    • at_least
    • goal
    • comment
    • name
    • per_instance
    • detect_overlap
  • Listing down cover points for a design
  • Instance coverage
  • Cross coverage with intersect
  • FC system task & Functions
  • Coverage Driven Verification
  • Coverage report analysis
  • Cover groups with arguments
  • Coverage filter using iff
  • Functional coverage types in TB
    • transaction class coverage
    • register field coverage
    • scenario coverage
  • Generating code coverage
  • Different types – FCBEST
    • FSM
    • Conditional
    • Branch
    • Expression
    • Statement
    • Toggle
  • Detailed understanding of code coverage types with examples
  • Merging UCDBs, generating coverage reports
  • Analyzing coverage report
  • Coverage exclusion
  • Need for assertions?
  • Assertion based verification
  • Types of assertions
  • Immediate assertions
  • Concurrent assertions
  • Assertion format – antecedent, consequent
  • Running assertions using questasim, debugging the assertions in waveform
  • Assertion hierarchy – property, sequence, boolean expression
  • ##, |-> and |=> operators
  • Assertion examples for clock frequency check
  • Assertion with local variables
  • Assertions for simple timing diagrams
  • Listing down and implementing assertions for simple designs
    • Async FIFO
    • Interrupt controller

System verilog constraints, randomization, coverage and assertions is a 30 hours course focused on practical usage of all language constructs. All constructs understood using hands on examples.
Above topics are among the most focused areas in design verification interviews. The course will help participants with lot of examples focused on interview focused questions.

CourseSV Constraints, randomization, Coverage and assertions – Deep dive
DurationLive training : 4 weeks
eLearning : 30 hours
Schedule 
Freshers6 days/week, 4 hours/day
Working professionalsSaturday & Sunday(9AM – 1PM IST)
Access to all course recorded videos for entire course duration
ToolQuestasim & VCS
Mode of trainingClassroom training & Live online training
Course can also be done in hybrid mode.
 eLearning with dedicated mentor for doubt clarifications.
FeeLive training : INR 5K + GST
eLearning : INR 4K + GST
Course Registration
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Course Highlights
  • 1-1 Dedicated Mentor Support
  •  24/7 Tool Access
  • Multiple mock interviews
  • Industry Standard Projects
  • Support with resume update