SOC Design and Verification

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SOC Design and Verification

  • RTL code freeze
  • Base tape out
  • Metal tape out
  • ECO update
  • CS (customer shipment)
  • RMA
  • SoC Architecture
  • SOC Design Integration
  • SoC Subsystems
  • Processor, High speed, Low speed, Modem, Multimedia subsystem
  • SoC Interconnects & NOCs
  • NoC Overview – Types of NOCs, purpose and diagram
  • SoC Digital & Analog Components
  • SOC UPF
  • Voltage domains
  • Power domains
  • Clock domains
  • Different clock mode – XO mode, at-speed mode
  • CDC
  • SoC Address Mapping
  • SoC Interrupt Mapping
  • SoC Frequency Plan
  • SoC Performance requirements
  • SoC Features
  • SoC Memories: Msg ram, Iram, DDR, Flash
  • GPIO purpose : Pad muxing
  • I/O’s of SOC: Dedicated IO’s, and GPIOs
  • Setting up environment
  • Processor boot concepts
  • Types of verification : how they are different
  • SoC Processor-TB interaction
  • How to set reset location to start booting.
  • Loading C code into memories – Front door, back door.
  • SCF file
  • SoC Architecture, understanding transaction matrix
  • SOC Test bench architecture
  • SoC environment structure
  • Setting up SOC TB environment
  • Using library functions to implement C test cases
  • Integrating UVC in Testbench setup
  • sequence usage in SV testcase
  • understanding handshake between Native & SV code
  • Functional Verification
  • Formal Verification (Connectivity Checks)
  • SOC Test plan
  • SOC Test case Flow
  • SOC Test case Coding (C files & SV files)
  • DDR initialization
  • Setting up regression
  • Running test cases & regression
  • SOC Test debug
  • Verification closure
  • Power Aware Simulations
  • Listing down test requirements, pass criteria
  • Functional test
  • register wr-rd, reset tests
  • Interrupt tests
  • targeting different frequency plans
  • Feature(use-case) tests
  • power aware tests
  • Fuse tests
  • End to end data transfer tests
  • Booting from different memories
  • Address decoding access tests
  • Connectivity tests
  • Power collapse and uncollapse tests
  • SOC testcase bring up
  • Memory preloading
  • Processor booting from different memories
  • TIC mode
  • PLL locking(LMN values)
  • Functional mode
  • Power domains to be up
  • clock domains to be up, required frequencies
  • Understanding required flow to implement testcase
  • Device Initialisation
  • DDR initialisation
  • Enabling DDR access to different processors
  • Processor boot sequence
  • Processor boot from different memories
  • C test Main function
  • Interrupt handler
  • tarmac log
  • List file
  • mpf file
  • Simulation log
  • Wave dump debug
  • Message based debug
  • Warnings, errors
  • Processor not booting
  • register looping
  • Not working at current frequency plan
  • pll not locked
  • Memory not preloaded
  • clocks not running
  • Access is not enabled to register or memory space
  • Simulation not proceeding in time
  • Simulation is proceeding in time but not completing (looping)
  • Interrupt not serviced
  • interrupt not generated
  • Signal not sampled
  • sub module functional issues
  • Denali errors
  • Memory loading ‘x’ debug
  • tied signals, unconnected ports
  • Cycle slips
  • Choosing tests for GLS
  • Vector generation
  • EVCD generation
  • Need for EVCD
  • Vector runs on VT setup
  • Generating binaries for running on tester
  • RMA
  • ECO
  • What stage ECO is issued
  • Vector debug
  • Significance
  • Format
  • Vector runs on VT setup
  • Production vectors
  • Characterization vectors
  • RMA
  • Design baseline
  • Updating env for custom baseline
  • all design sub component latest baselines
  • verif baseline
  • Command line
  • sim_gui mode
  • Command line options
  • using force files, timing corners, frequency plans
  • ARM, ARC, DSP
  • Processor architectures
  • Impact on design architecture
  • Basics of ARM processors
  • ARM processor types – Cortex-M series, A series.
  • Processor interfaces: interfaces meant for fetching instruction, data code
  • MMU, Physical address, virtual address
  • ARM instruction set basics
  • ARM C, ASM compiler, linker.
  • Caches (L1 and L2).
  • Generic Interrupt controller.
  • Exceptions, Events – Types of Exceptions (Edge, Level), Source of Exceptions, How to handle.
  • Debug system – Basics of ARM debug sub system.
  • Scatter files.
  • ARM Instruction example
  • UPF
  • PA RTL simulations
  • PA GLS simulations
  • Vector evcd generation
  • VT simulations on testers
  • Post silicon validation
  • TIC interface
  • JTAG
  • Debug
  • Regression 100% pass
  • 100% toggle coverage
  • reviews high level & low level
  • Performance requirements
  • Power requirements met

At least 60% of functional verification work in VLSI is based on SOC & Subsystem verification. It is essential for every verification engineer to gain expertise on SoC & Subsystem verification concepts. The course is for functional verification engineers with module level verification expertise and planning to explore SOC verification. This course is essential for every verification engineer with 5+ years of experience have never got exposure to SOC verification.

Currently there is no live sessions planned. You may enroll for eLearning Course for self-paced learning, with option to join upcoming batch with no additional cost.

CourseSoC Design & Verification
Duration7 weeks
Next Batch 
Demo Session 
Registration 
Schedule 
Course repeatsevery 10 weeks
Fee

Elearning Training 11,000 + GST at 18%

Live Training 13,000 + GST at 18%

ToolQuestasim, Kiel
Mode of trainingClassroom training at VLSIGuru Institute, Banaswadi, ORR
 Online training using live training sessions
CertificateIssued based on 50% assignment completion as criteria
Batch Size20
Assignments20
Trainer12+ Years exp in RTL design & Functional verification
Course Registration
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Course Highlights
  • 1-1 Dedicated Mentor Support
  •  24/7 Tool Access
  • Multiple mock interviews
  • Industry Standard Projects
  • Support with resume update