• Czachorowski (CZ) Process
• Lithography
• Oxidation
• Overview of Process
• CMOS fabrication sequence
• OPC
• Process rules
• Resistor cross section
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• IC design tech nodes and challenges
• Common analog design topologies
• Layout work ow:
  
  • Schematic-Schematic capturing, Reading the Schematic Components.
  • Layout -Floor-planning, Series and Parallel devices (Mos, Res and Cap), Placement, Routing
  • Physical Verification- Design Rule Check Layout vs Schematic.
  • Process Design Kit- Process Document, Rule file for all verification, Model libraries

• Digital Cells Layout,
• Digital cell library, Digital Cells Examples,
• Stick diagram, Euler path,
• Digital Cell Design and Routing: Routing, Digital Cell P&R Particulars, Metal Spacing Grids,
• Digital Cell Template, Guidelines to Layout Std. Cell Lib, Schematic for adder

• Analog vs Digital
• Devices sizes in Analog Layout
• Fingers and Multipliers
• Analog Layout: Matching, Methods of Matching, Inter-digitized, Common Centroid, Guidelines Matching
• Analog Layout Challenges: Electromigration, Electromigration – Flow, Electromigration – Layo care, IR Voltage drop, Latch-Up, ESD, Antenna Effect, Coupling & Shielding, Shallow Trench
  Isolation, Well Proximity Effect,
• Multi Domain Power and Ground, Cross Section of cascade devices, Deep Newell, Separate potential Newell, Cross Section with Drawn Layers,

Well structures, Deep Newell/Tripple well process, Level shifter, Planar MOSFET Vs Finet, Fabrication, Layout challenges