Verilog

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Verilog

  • Verilog language basics
  • Verilog: How the language evolved?
  • Verilog execution using Modelsim
  • Verilog constructs
    • Literals
    • Data types
    • registers, nets
    • Vectors, Array
    • Operators
    • Various styles of Modeling: Data Flow, Behavioral, Gate level, Switch level
    • Continuous assignments
    • Combinational logic coding : Half adder, full adder, multiplexer, comparator, encoder, decoder, priority encoder
    • Generate
    • Procedural timing controls
    • task and functions
    • system task and function
    • modeling memories and FSM
    • Parameters
    • Port connections
    • Procedural blocks
    • Sensitivity list
    • State machines
    • timescale
    • Verilog timing regions
    • process
    • Blocking and nonblocking statements
    • Inferring combinational and Sequential logic
    • Clock generation with Duty cycle & Jitter
    • Shift register implementation
    • Procedural Blocks
    • fork join
    • Race conditions
    • Synthesis examples
    • Inter and Intra delay statements
    • example to showcase race condition using blocking assignments
    • Pipelining
    • Memories
    • Structural modeling
    • Verilog Programming Interface(& PLI)
    • PLI
    • compiler directives
    • system task usage: $display, $monitor, $strobe
    • PLI, VPI implementation
    • Primitive implementation using table, endtable
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  • DFF coding using gate level, behavioral
  • Counters
    • Up counter
    • Ring counter
    • Johnson counter
  • Memory RTL coding and TB development
    • Memory Verilog coding
    • Declaring a parameterized memory
    • Front door access
    • Back door access test case coding
    • Implemneting task for front door and back door access
    • Test case coding and understanding waveforms
  • FIFO – Synchronous FIFO and Asynchronous FIFO
    • Synchronous FIFO
    • Asynchronous FIFO
  • Finite state machines
    • Mealy and Moore style
    • Implicit and Explicit styles of coding.
  • Pattern detector – Overlapping, Non-Overlapping, Dynamic
    • Overlapping
    • Non-Overlapping
    • Dynamic
  • Traffic light controller
  • APB protocol
  • Interrupt controller
  • SPI controller
  • CRC generation

Verilog for Design & Verification is a 10 weeks course with detailed emphasis on Verilog for complex design implementation and verification. Verilog course helps both design and verification engineers to gain expertise in Verilog for RTL coding and test bench development. 

Every aspect of Verilog course is supported with multiple examples to make the learning easier. Course also covers multiple design implementation examples and test bench setup for the same, and all these done from scratch. 

Lab sessions are planned everyday to enable student work on these projects from scratch with trainer guidance. 

CourseVerilog for Design & Verification
Duration9 weeks
  
Schedule 
Freshers6 days/week, 4 hours/day
Working professionalsSaturday & Sunday(9AM – 1PM IST)
Access to all course recorded videos for entire course duration
ToolQuestasim & VCS
Mode of trainingClassroom training & Live online training
Course can also be done in hybrid mode.
 eLearning with dedicated mentor for doubt clarifications.
FeeLive training : INR 14K + GST
eLearning : INR 12K + GST
Batch Size25
Assignments23
Course Registration
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Course Highlights
  • 1-1 Dedicated Mentor Support
  •  24/7 Tool Access
  • Multiple mock interviews
  • Industry Standard Projects
  • Support with resume update