UPF Power Aware Verification
Course Summary
- Power Management – Need for low power
- CMOS basics w.r.t Power Consumption
- Low Power Techniques
- SoC and PMIC architectures
- UPF Concepts
- UPF design data flow
- UPF Power Intent commands
- Memory Controller architecture
- Memory Controller low power verification setup
- Running low power simulations
- How to debug low power issues
- Low power assertions and coverage
- Â
Power consumption is significant aspect of increasingly complex SOCs, which are typically used for portable systems. Low power design techniques helps identify the power behavior and minimise the power consumption. Both portable and non-portable systems, requires efficient power management techniques.
This course introduces IEEE 1801 UPF for specifying the idle power management architecture.
Student will learn SoC power domain architecture , in UPF how to define power intent – supply_port, supply_net, power cells like power switches, isolation cells, level shifters , retention cells, power state table and gating logic. They will also learn how to update a design for the power intent, run the simulation to analyse the power behavior.
| Course | Power aware UPF verification |
|---|---|
| Duration | Live training : 3 weeks eLearning : 14 hours |
| Next Batch | Â |
| Schedule | Saturday, Sunday, 9AM to 1PM |
| Tool | Questasim & VCS |
| Mode of training | Live training for a minimum of 10 participants. eLearning mode. |
| Fee | Live training : INR 6K + GST eLearning : INR 4.5K + GST |
Course Highlights
- 1-1 Dedicated Mentor Support
- Â 24/7 Tool Access
- Multiple mock interviews
- Industry Standard Projects
- Support with resume update