Design for Testability (DFT)

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Design for Testability (DFT)

  • ASIC Flow
  • DFT Basics
  • Chip Fabrication Process
  • ATE Basics
  • Scan architecture overview
  • Scan Design Basics
  • Scan Golden Rules
  • Scan DRC Checks
  • Scan Insertion
  • Generate test protocol and understanding
    Lock-Up Latches
  • Basics/Need for Compression
  • Compression Techniques
  • On-Chip-Clocking
  • At-Speed Testing
  • Hierarchical Scan
  • Bscan (Boundary Scan)
  • Jtag
  • ATPG Basics
  • Faults Collapsing
  • ATPG Algorithms
  • Fault Models,
  • ATPG DRC,
  • Fault Classes,
  • ATPG
  • Simulation Basics
  • Atpg Simulations
  • Coverage Improvement
  • At-Speed ATPG
  • LOC and LOS
  • At-Speed Simulations
  • Scan Simulations Debug
  • Diagnosis Flow
  • Fault Simulation
  • BIST Architecture,
  • Memory BIST
  • Logic BIST
  • A block-level design will be given as project, in which you need to insert scan and generate patterns, to get the required test coverage.

VLSI professionals can build a rewarding and challenging career with DFT Online Course and DFT Training.


Design For Testability, commonly called as DFT is a specialization in the SOC design cycle, which facilitates design for detecting manufacturing defects. DFT Course is different than functional verification, which tests the functionality of the design and is popularly known as Design Verification.


VLSI DFT Course online has evolved as a specialization in itself over period of time, with the increase in size & complexity of chips, facilitated by the advancement of manufacturing technologies like 10nm, 7nm, DFT Engineers works on introducing various test structures as part of the design flow, on increasing the testability of logic, pads, memories, interconnects.


DFT Course Online covers different techniques like Scan Insertion to test the combinational & sequential logic, BIST to test the memories, JTAG to test the PADS. etc. Using ATPG Techniques test patterns are generated on the scan inserted design. Generated patterns are simulated and debugged in case of any failures.

VLSI DFT Course Online is designed as per industry requirements, covering SCAN, ATPG, BIST, JTAG along HandsOn labs and multiple projects covering all DFT Techniques.

Duration16 weeks
Next Batch 
Schedule

Saturday & Sunday

9AM – 1PM, theory sessions

2PM to 6PM, lab sessions

Course repeatsevery 8 weeks
ToolMentor Graphics Tessent, Synopsys DFTAdvisor and Tetramax
Mode of trainingBoth Classroom training and live online training
 e-learning course for self paced learning
Tool AccessTool access for the complete course duration
CertificateCourse completion certificate issued
Batch Size20
Assignments20
Course Registration
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Course Highlights
  • 1-1 Dedicated Mentor Support
  •  24/7 Tool Access
  • Multiple mock interviews
  • Industry Standard Projects
  • Support with resume update