• Number System, Boolean Algebra, SOP and POS, K-Map
• Combinational circuits
• Sequential circuits
• Finite State machines
• Frequency Division
• Setup and Hold time checks
• Advance Design Issues: Metastability, Noise Margins, Power, Fanout, Timing
• Considerations
• FIFO Depth Calculation
• Assessment and Quizzes

• Electronic Devices, Power Sources, Thevenin and Norton Theorem
• Semiconductors Device Physics: Atomic Structure, Electronic Configuration, Doping, Diode –Biasing and VI Characteristics
• MOSFET: Regions of operation, VI Characteristics
• Function implementation using CMOS
• Stick Diagram and Layout
• Second order effects: Body Effect, Channel length modulation, Punch through, subthreshold conduction, DIBL
• Process Technology: Clean Room, Wafer manufacturing, Oxidation, Diffusion, Ion
  Implementation, Lithography
• Assessment and Quizzes

• Introduction to Verilog
• Applications of Verilog HDL
• Verilog HDL language concepts
• Verilog language basics and constructs
• Data Types, Nets and registers, Arrays
• Verilog Operators: Logical operators, Bitwise and Reduction operators, Concatenation and conditional operators, Relational and arithmetic, Shift and Equality operators, Operators precedence.
• Type of assignments: Continuous assignments, Inter/Intra assignments, Blocking and Nonblocking assignments, Execution branching, Tasks and Functions
• Finite State Machine (FSM): Basic FSM structure, Moore Vs Mealy, Common FSM coding styles, Registered outputs
• Assessment and Quizzes

• ASIC Design flow and role of Synthesis
• Synthesis flow
• writing timing constraints in SDC format
• constraining the design for timing
• power, area goals, set optimization techniques
• synthesize the design
• generate and analyze the reports, save the netlist and SDC

• Formal Verification
• Understanding & Matching compare points
• Debugging nonequivalent points What-If Analysis

Features of TCL and Applications. TCL commands, Variables, arithmetic expressions, comments, identifiers, reserved words, data types, decisions, loops, arrays, strings, file I/O and procedures.

Scripting exercises from simple problems to complex problems, in an incremental manner and
using tools like Prime Time, ICC2.

Introduction to physical design and Physical Design Flow, Data preparation: Files required for PD (Netlist, SDC, Libraries, Technology files, TLU+), the contents of each input file, Sanity checks.

Goals of Floor planning, different aspects of floor planning, Rectangle/Rectilinear floorplans, Die
size estimation (Core Utilization, Aspect ratio), IO placement, macro placement and guidelines,
channel-width estimation

Goals of Power Routing, Power distribution structure (Rings, straps and follow-pin/std cell rail), metal stack information, power planning methodology, IR drop analysis, types of power
consumption. Why Low power and low power techniques. Electro-migration analysis.

Goals of Placement, types of placements, pre-place (Endcap, Tap & I/O Buffer) cells, placement optimization, congestion analysis, timing analysis, Tie-cells, High-Fanout Net Synthesis, Scan chain re-order, Path Grouping and creating Bounds.

STA Overview and concepts, Basic timing checks (setup, hold), understanding timing
constraints (SDC), timing corners, timing report analysis.

General optimization techniques, typical causes for timing violations and strategies for fixing the
same, Pre-CTS optimization to Fix setup violation

Goals of CTS, Types of Clock-tree, constraints for CTS, building clock tree, Analyze the results,
Post-CTS optimization: Fixing Setup and Hold violations.

Goals of Routing, Stages of Routing: Global Routing, Track assignment and Detail Routing,
Routing options, Fixing of routing violations (DRC, LVS), post route optimization, issues in routing and guidelines for optimum routing results.

Post layout STA using SPEF, Multi-Mode Multi Corner STA, Derating factors, PVT, OCV Variations, Crosstalk Analysis

What is ECO, Types of ECO, Timing & Functional ECO, Performing the ECO placement and routing.